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Gary Spivey > Text-EP3-Verilog > Text::EP3::Verilog



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Text::EP3::Verilog - Verilog extension for the EP3 preprocessor.


  use Text::EP3;
  use Text::EP3::Verilog;


This module is an EP3 extension for the Verilog Hardware Description Language.

The signal directive

@signal key definition Take a list of signals and generate signal lists in the differing formats that Verilog uses. This is accomplished by formatting a list of new defines and then calling the EP3 define method For example, the following command:

        @signal KEY a[3:0], b, c[width:0], etc.

will cause the following to be done:

        Define KEY with the list as it appears (can be used in further signal defs)
        Define KEY{SIG} with the signal list (can be used in port lists)
        e.g. replace KEY{SIG} with  a[3:0], b, c[width:0]
        Define KEY{EVENT} with the reg list  (To be used in event lists)
        e.g. replace KEY{EVENT} with a or b or c
        Define KEY{IN}  with the input list (you supply the first input and the trailing ';'
        e.g. replace KEY{INPUT} with [3:0] a;\ninput b;\ninput[width:0] c
        or ... make the line 
        input KEY{INPUT}; become ..
        input [3:0] a;
        input b;
        input [width:0] c;
        Define KEY{OUT} with the output list (output [] sig).
        e.g. like KEY{IN}
        Define KEY{INOUT}  with the inout list (inout [] sig).
        e.g. like KEY{IN}
        Define KEY{WIRE} with the wire list (wire [] sig).
        e.g. like KEY{IN}
        Define KEY{REG} with the reg list (reg [] sig).
        e.g. like KEY{IN}
        Define KEY{DSP} with the printf list (sig=%0[b|x] depending on width).
        e.g. replace KEY{DSP} with a=%0x, b=%0b, c=%0x
        This can be used in the $display task

If the module and the test bench default is set up properly, the user needs only enter the signals in one place in the module file. This section can be included conditionally (e.g. @include "file" PORT) in the test bench and the signals can be automatically generated in the correct format in whichever header they are used. This means that a user can produce a module and its test bench by simply filling in the port list, the behavioral code, and the stimulus (which is of course, the real work). All of the signal header crud can be taken care of automagically.

The step directive

@step number [command] The step directive is useful to save verbage in test benches. @step 5 command; generates the following code:

        repeat 5 @ (posedge tclk); command;

The posdege can be changed to '' or negedge (or whatever) using the edgetype directive. The tclk can be changed using the edgename directive.

The edgename directive

@edgename name The edgename directive allows the user to change the name used in the step directive. The default is 'tclk'.

The edgetype directive

@edgetype type The edgetype directive allows the user to change the type used in the step directive. The default is 'posedge'.

The denum directive

@denum key, key, [value], key, ... denum works like the ep3 enum, except that it generates verilog define statements. It also replaces KEY anywhere in the text with `KEY so that the verilog defines will work. (e.g. @denum orange, blue, green will generate:

        `define orange 0
        `define blue 0
        `define green 0
        @define orange `orange
        @define blue `blue
        @define green `green


Gary Spivey, Dept. of Defense, Ft. Meade, MD.



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