| This Release | Verilog-Perl-3.401 | [Download] [Browse] | 21 May 2013 | |||
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| Links | [ Discussion Forum ] [ View/Report Bugs ] [ Website ] [ Dependencies ] [ Other Tools ] | |||||
| CPAN Testers | PASS (65) UNKNOWN (184) [ View Reports ] [ Perl/Platform Version Matrix ] | |||||
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| License | The Perl 5 License (Artistic 1 & GPL 1) | |||||
| Special Files |
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| Verilog::EditFiles | Split Verilog modules into separate files. | 3.401 | |
| Verilog::Getopt | Get Verilog command line options | 3.401 | |
| Verilog::Language | Verilog language utilities | 3.401 | |
| Verilog::Netlist | Verilog Netlist | 3.401 | |
| Verilog::Netlist::Cell | Instantiated cell within a Verilog Netlist | 3.401 | |
| Verilog::Netlist::ContAssign | ContAssign assignment | 3.401 | |
| Verilog::Netlist::Defparam | Defparam assignment | 3.401 | |
| Verilog::Netlist::File | File containing Verilog code | 3.401 | |
| Verilog::Netlist::Interface | Interface within a Verilog Netlist | 3.401 | |
| Verilog::Netlist::Logger | Error collection and reporting | 3.401 | |
| Verilog::Netlist::ModPort | ModPort within a Verilog Interface | 3.401 | |
| Verilog::Netlist::Module | Module within a Verilog Netlist | 3.401 | |
| Verilog::Netlist::Net | Net for a Verilog Module | 3.401 | |
| Verilog::Netlist::Pin | Pin on a Verilog Cell | 3.401 | |
| Verilog::Netlist::Port | Port for a Verilog Module | 3.401 | |
| Verilog::Netlist::Subclass | Common routines for all classes | 3.401 | |
| Verilog::Parser | Parse Verilog language files | 3.401 | |
| Verilog::Preproc | Preprocess Verilog files | 3.401 | |
| Verilog::SigParser | Signal Parsing for Verilog language files | 3.401 | |
| Verilog::Std | SystemVerilog Built-in std Package Definition | 3.401 |
| Verilog-Perl | Overview of Verilog language packages for Perl |
| bisonpre | Bison wrapper with pre and post processing |
| callbackgen | Create callback functions for Verilog-Perl internals |
| toolhash | Generate and hash files to avoid installation of build tools |
| vhier | Return all files in a verilog hierarchy using Verilog::Netlist |
| vpassert | Preprocess Verilog code assertions |
| vppreproc | Preprocess Verilog code using verilog-perl |
| vrename | change signal names across many Verilog files |
