The Perl Toolchain Summit needs more sponsors. If your company depends on Perl, please support this very important event.

Search results for "GSULLIVAN"

Verilog::VCD - Parse a Verilog VCD text file River stage zero No dependents

Verilog is a Hardware Description Language (HDL) used to model digital logic. While simulating logic circuits, the values of signals can be written out to a Value Change Dump (VCD) file. This module can be used to parse a VCD file so that further ana...

GSULLIVAN/Verilog-VCD-0.08 - 04 May 2018 14:48:07 UTC - Search in distribution

convert_eng - Convert numbers to and from engineering notation River stage one • 1 direct dependent • 1 total dependent

Format a number (or a list of numbers) using engineering notation. Formatted/converted values will be printed to STDOUT, one per line....

GSULLIVAN/Number-FormatEng-0.03 - 07 Nov 2017 13:58:40 UTC - Search in distribution

YAPE::Regex - Yet Another Parser/Extractor for Regular Expressions River stage one • 3 direct dependents • 3 total dependents

This module is yet another (?) parser and tree-builder for Perl regular expressions. It builds a tree out of a regex, but at the moment, the extent of the extraction tool for the tree is quite limited (see "Extracting Sections"). However, the tree ca...

GSULLIVAN/YAPE-Regex-4.00 - 03 Feb 2011 14:01:00 UTC - Search in distribution

Text::Banner - Create text resembling Unix banner command River stage one • 1 direct dependent • 3 total dependents

The Text::Banner creates a large ASCII-representation of a defined string, like the 'banner' command available in Unix. A string is passed to the module, and the equivalent banner string is generated and returned for use. The string can be scaled (bl...

GSULLIVAN/Text-Banner-2.01 - 04 Nov 2015 21:38:56 UTC - Search in distribution

Verilog::Readmem - Parse Verilog $readmemh or $readmemb text file River stage zero No dependents

The Verilog Hardware Description Language (HDL) provides a convenient way to load a memory during logic simulation. The "$readmemh()" and "$readmemb()" system tasks are used in the HDL source code to import the contents of a text file into a memory v...

GSULLIVAN/Verilog-Readmem-0.05 - 09 Jul 2015 14:26:47 UTC - Search in distribution

String::LCSS - Find The Longest Common Substring of Two Strings. River stage one • 1 direct dependent • 1 total dependent

String::LCSS provides the function "lcss" to ferret out the longest common substring shared by two strings passed as arguments....

GSULLIVAN/String-LCSS-1.00 - 01 Jan 2016 00:44:41 UTC - Search in distribution

YAPE::Regex::Explain - explanation of a regular expression River stage zero No dependents

This module merely sub-classes "YAPE::Regex", and produces a rather verbose explanation of a regex, suitable for demonstration and tutorial purposes. Methods for "YAPE::Regex::Explain" * "my $p = YAPE::Regex::Explain->new($regex);" Calls "YAPE::Regex...

GSULLIVAN/YAPE-Regex-Explain-4.01 - 14 Sep 2010 17:58:47 UTC - Search in distribution
7 results (0.027 seconds)