Search results for "module:Verilog::Parser"
Verilog::Parser - Parse Verilog language files
Verilog::Parser will tokenize a Verilog file when the parse() method is called and invoke various callback methods. This is useful for extracting information and editing files while retaining all context. For netlist like extractions, see Verilog::Ne...
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Hardware::Verilog::Parser - A complete grammar for parsing Verilog code using perl
This module defines the complete grammar needed to parse any Verilog code. By overloading this grammar, it is possible to easily create perl scripts which run through Verilog code and perform specific functions. For example, a Hierarchy.pm uses Hardw...
GSLONDON/Hardware-Verilog-Parser-0.13 - 27 Apr 2000 13:18:31 UTC
Verilog::SigParser - Signal Parsing for Verilog language files
Verilog::SigParser builds upon the Verilog::Parser module to provide callbacks for when a signal is declared, a module instantiated, or a module defined. See the "Which Package" section of Verilog::Language if you are unsure which parsing package to ...
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::Netlist::File - File containing Verilog code
Verilog::Netlist::File allows Verilog::Netlist objects to be read and written in Verilog format....
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::Netlist - Verilog Netlist
Verilog::Netlist reads and holds interconnect information about a whole design database. See the "Which Package" section of Verilog::Language if you are unsure which parsing package to use for a new application. A Verilog::Netlist is composed of file...
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::Preproc - Preprocess Verilog files
Verilog::Preproc reads Verilog files, and preprocesses them according to the SystemVerilog 2009 (1800-2009) specification. Programs can be easily converted from reading a IO::File into reading preprocessed output from Verilog::Preproc. See the "Which...
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::Language - Verilog language utilities
Verilog::Language provides general utilities for using the Verilog Language, such as parsing numbers or determining what keywords exist. General functions will be added as needed....
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC