Search results for "module:Verilog::SigParser"
Verilog::SigParser - Signal Parsing for Verilog language files
Verilog::SigParser builds upon the Verilog::Parser module to provide callbacks for when a signal is declared, a module instantiated, or a module defined. See the "Which Package" section of Verilog::Language if you are unsure which parsing package to ...
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::Std - SystemVerilog Built-in std Package Definition
Verilog::Std contains the built-in "std" package required by the SystemVerilog standard....
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::Parser - Parse Verilog language files
Verilog::Parser will tokenize a Verilog file when the parse() method is called and invoke various callback methods. This is useful for extracting information and editing files while retaining all context. For netlist like extractions, see Verilog::Ne...
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC