Search results for "module:Verilog::Language"
Verilog::Language - Verilog language utilities
Verilog::Language provides general utilities for using the Verilog Language, such as parsing numbers or determining what keywords exist. General functions will be added as needed....
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::Parser - Parse Verilog language files
Verilog::Parser will tokenize a Verilog file when the parse() method is called and invoke various callback methods. This is useful for extracting information and editing files while retaining all context. For netlist like extractions, see Verilog::Ne...
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::VCD - Parse a Verilog VCD text file
Verilog is a Hardware Description Language (HDL) used to model digital logic. While simulating logic circuits, the values of signals can be written out to a Value Change Dump (VCD) file. This module can be used to parse a VCD file so that further ana...
GSULLIVAN/Verilog-VCD-0.08 - 04 May 2018 14:48:07 UTC
Verilog::SigParser - Signal Parsing for Verilog language files
Verilog::SigParser builds upon the Verilog::Parser module to provide callbacks for when a signal is declared, a module instantiated, or a module defined. See the "Which Package" section of Verilog::Language if you are unsure which parsing package to ...
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::Std - SystemVerilog Built-in std Package Definition
Verilog::Std contains the built-in "std" package required by the SystemVerilog standard....
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::Getopt - Get Verilog command line options
Verilog::Getopt provides standardized handling of options similar to Verilog/VCS and cc/GCC....
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::Readmem - Parse Verilog $readmemh or $readmemb text file
The Verilog Hardware Description Language (HDL) provides a convenient way to load a memory during logic simulation. The "$readmemh()" and "$readmemb()" system tasks are used in the HDL source code to import the contents of a text file into a memory v...
GSULLIVAN/Verilog-Readmem-0.05 - 09 Jul 2015 14:26:47 UTC
Verilog::Preproc - Preprocess Verilog files
Verilog::Preproc reads Verilog files, and preprocesses them according to the SystemVerilog 2009 (1800-2009) specification. Programs can be easily converted from reading a IO::File into reading preprocessed output from Verilog::Preproc. See the "Which...
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Verilog::Netlist - Verilog Netlist
Verilog::Netlist reads and holds interconnect information about a whole design database. See the "Which Package" section of Verilog::Language if you are unsure which parsing package to use for a new application. A Verilog::Netlist is composed of file...
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC
Text::EP3::Verilog - Verilog extension for the EP3 preprocessor.
This module is an EP3 extension for the Verilog Hardware Description Language. The signal directive @signal key definition Take a list of signals and generate signal lists in the differing formats that Verilog uses. This is accomplished by formatting...
GSPIVEY/Text-EP3-Verilog-1.00 - 13 Mar 1998 20:00:12 UTC
Verilog::VCD::Writer - VCD waveform File creation module.
This module originated out of my need to view the <Time,Voltage> CSV dump from the scope using GTKWave. This module provides an interface for creating a VCD (Value change Dump) file. Please see examples/serial.pl for a complete example new (timescale...
JVS/Verilog-VCD-Writer-0.004 - 13 Dec 2017 03:21:45 UTC
Hardware::Verilog::Parser - A complete grammar for parsing Verilog code using perl
This module defines the complete grammar needed to parse any Verilog code. By overloading this grammar, it is possible to easily create perl scripts which run through Verilog code and perform specific functions. For example, a Hierarchy.pm uses Hardw...
GSLONDON/Hardware-Verilog-Parser-0.13 - 27 Apr 2000 13:18:31 UTC
Verilog::VCD::Writer::Module - Module abstraction layer for Verilog::VCD::Writer
JVS/Verilog-VCD-Writer-0.004
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13 Dec 2017 03:21:45 UTC
Verilog::VCD::Writer::Signal - Signal abstraction layer for Verilog::VCD::Writer
This module is designed to be called from the Verilog::VCD::Writer::Module module....
JVS/Verilog-VCD-Writer-0.004 - 13 Dec 2017 03:21:45 UTC