Search results for "Netlist"
Verilog::Netlist - Verilog Netlist
Verilog::Netlist reads and holds interconnect information about a whole design database. See the "Which Package" section of Verilog::Language if you are unsure which parsing package to use for a new application. A Verilog::Netlist is composed of file...
WSNYDER/Verilog-Perl-3.482 - 23 Jan 2024 02:49:53 UTC - Search in distribution- Verilog::Netlist::Pin - Pin on a Verilog Cell
- Verilog::Netlist::Net - Net for a Verilog Module
- Verilog::Netlist::Cell - Instantiated cell within a Verilog Netlist
- 15 more results from Verilog-Perl ยป
spice - interface calls for parsing spice netlst.
CALLING spice.pm ROUTINES This package only cares about m, R, C, X, and subckts. spice-decks are ignored. This priliminary version of spice supports following subroutine calls- @subckt = getTopSubckts ( ) ; returns a list of subckts, top in the hiera...
SROHIT/Spice-0_01 - 07 Sep 2000 18:17:02 UTC - Search in distribution
Verilog::CodeGen - Verilog code generator
Provides an object-oriented environment to generate Verilog code for modules and testbenches. The Verilog::CodeGen module provides two functions, one to create a code template and another to create a Perl module which contains the device library. Thi...
WVDB/Verilog-CodeGen-0.9.4 - 09 May 2003 14:55:35 UTC - Search in distribution