Interface:sv_if_ported  File:verilog/v_sv_mod.v
  Port:clk  Dir:in  DataT:  Array:
  Net:clk  O  DeclT:port  NetT:  DataT:  Array:
Interface:v_sv_intf  File:verilog/v_sv_intf.v
  Net:byte_port    DeclT:var  NetT:  DataT:v_sv_pkg::byte_t  Array:
  Cell:subintf  is-a:v_sv_intf2
            Interface:v_sv_intf2  File:verilog/v_sv_intf.v
    Pin:*  Net:*
Interface:v_sv_intf2  File:verilog/v_sv_intf.v
  Net:byte_port    DeclT:var  NetT:  DataT:v_sv_pkg::byte_t  Array:
  ModPort:Master  File:verilog/v_sv_intf.v
    Port:addr  Dir:out  DataT:  Array:
    Port:data  Dir:in  DataT:  Array:
Module:v_sv_mod  Kwd:module  File:verilog/v_sv_mod.v
  Port:clk  Dir:in  DataT:  Array:
  Port:intf  Dir:interface  DataT:v_sv_intf  Array:
  Net:clk  IO  DeclT:port  NetT:  DataT:  Array:
  Net:intf    DeclT:port  NetT:  DataT:v_sv_intf  Array:
  Cell:if_ported  is-a:sv_if_ported
            Interface:sv_if_ported  File:verilog/v_sv_mod.v
    Pin:clk  Net:clk
              Port:clk  Dir:in  DataT:  Array:
              Net:clk  IO  DeclT:port  NetT:  DataT:  Array:
  Cell:intf  is-a:v_sv_intf
            Interface:v_sv_intf  File:verilog/v_sv_intf.v
  Cell:pgm  is-a:v_sv_pgm
            Module:v_sv_pgm  Kwd:program  File:verilog/v_sv_pgm.v
Module:v_sv_pgm  Kwd:program  File:verilog/v_sv_pgm.v