`line 1 "verilog/t_80_foo.v" 1
// DESCRIPTION: Verilog::Preproc: Example source code
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012-2012 by Wilson Snyder.
//
// Test -F option in vppreproc.
// This is the top level module.

module foo(output wire y, input wire x);
   bar i_bar(y, x);
endmodule // foo

`line 12 "verilog/t_80_foo.v" 2
`line 1 "verilog/t_80_bar/bar.v" 1
// DESCRIPTION: Verilog::Preproc: Example source code
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2012-2012 by Wilson Snyder.
//
// Test -F option in vppreproc.

module bar(output wire y, input wire x);
   assign y = x;
endmodule // bar

`line 11 "verilog/t_80_bar/bar.v" 2
`line 1 "verilog/inc2.v" 1
// DESCRIPTION: Verilog::Preproc: Example source code
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2000-2012 by Wilson Snyder.
At file "verilog/inc2.v"  line 4
 
`line 5 "verilog/inc2.v" 0
`line 1 "verilog/t_preproc_inc3.vh" 1
`line 2 "inc3_a_filename_from_line_directive" 0
// DESCRIPTION: Verilog::Preproc: Example source code
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2000-2012 by Wilson Snyder.

 
  
  
  // FOO
  At file "inc3_a_filename_from_line_directive"  line 10

   
 // guard

 
  


`line 19 "inc3_a_filename_from_line_directive" 2
`line 5 "verilog/inc2.v" 0

  
`line 7 "verilog/inc2.v" 2