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// DESCRIPTION: Verilog-Perl: Example Verilog for testing package
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2010-2012 by Wilson Snyder.

module 51_vrename_kwd;
   wire do = bar;
   wire \esc[ape]d = bar;
   wire \do = bar;
   initial $display("bar");
   initial $display("bar.bar");
   initial $display("baz_foo");
   initial $display("foo_baz");
endmodule