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WSNYDER / Verilog-Perl-3.446 / t / 30_preproc_nows.out 
verilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc1.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc2.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc_ifdef.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 1
verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0
verilog/inc_nonl.v:1: `line 1 "verilog/inc_def09.v" 1
verilog/inc_def09.v:11: 'initial $display("start", "msg1" , "msg2", "end");'
verilog/inc_def09.v:12: 'initial $display("start", "msg1" , "msg2" , "end");'
verilog/inc_def09.v:13: 'initial $display("start", " msg1" , , "end");'
verilog/inc_def09.v:14: 'initial $display("start", " msg1" , , "end");'
verilog/inc_def09.v:15: 'initial $display("start", , "msg2 ", "end");'
verilog/inc_def09.v:16: 'initial $display("start", , "msg2 ", "end");'
verilog/inc_def09.v:17: 'initial $display("start", , , "end");'
verilog/inc_def09.v:18: 'initial $display("start", , , "end");'
verilog/inc_def09.v:19: 'initial $display("start", , , "end");'
verilog/inc_def09.v:20: 'initial $display("start", , , "end");'
verilog/inc_def09.v:27: '$display(5,,2,,3);'
verilog/inc_def09.v:28: '$display(5,,2,,3);'
verilog/inc_def09.v:29: '$display(1,,"B",,3);'
verilog/inc_def09.v:30: '$display(1 ,,"B",,3 );'
verilog/inc_def09.v:31: '$display(5,,2,,);'
verilog/inc_def09.v:32: '$display(5,,2,,);'
verilog/inc_def09.v:36: '$display(1,,,,3);'
verilog/inc_def09.v:37: '$display(5,,,,"C");'
verilog/inc_def09.v:38: '$display(5,,2,,"C");'
verilog/inc_def09.v:39: '$display(5,,2,,"C");'
verilog/inc_def09.v:40: '$display(5,,2,,"C");'
verilog/inc_def09.v:41: '$display(5,,2,,"C");'
verilog/inc_def09.v:44: '$display(1,,0,,"C");'
verilog/inc_def09.v:45: '$display(1 ,,0,,"C");'
verilog/inc_def09.v:46: '$display(5,,0,,"C");'
verilog/inc_def09.v:47: '$display(5,,0,,"C");'
verilog/inc_def09.v:51: 'b + 1 + 42 + a'
verilog/inc_def09.v:52: 'b + 1 + 42 + a'
verilog/inc_def09.v:56: '"==)" "((((" () ';
verilog/inc_def09.v:57: '"==)" "((((" () ';
verilog/inc_def09.v:70: '(6) (eq=al) ZOT'
verilog/inc_def09.v:71: HERE-71 - Line71
verilog/inc_def09.v:75: `line 75 "verilog/inc_def09.v" 2
verilog/inc_nonl.v:1: `line 1 "verilog/inc_nonl.v" 0
verilog/inc_nonl.v:2: blah-no-newline-here>
verilog/inc_nonl.v:3: `line 3 "verilog/inc_nonl.v" 2
verilog/inc_ifdef.v:1: `line 1 "verilog/inc_ifdef.v" 0
verilog/inc_ifdef.v:12:  $display("1A");
verilog/inc_ifdef.v:16:  $display("2A");
verilog/inc_ifdef.v:22:  $display("3AELSE");
verilog/inc_ifdef.v:42: `line 42 "verilog/inc_ifdef.v" 2
verilog/inc2.v:1: `line 1 "verilog/inc2.v" 0
verilog/inc2.v:4: At file "verilog/inc2.v" line 4
verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0
verilog/inc2.v:5: `line 1 "verilog/t_preproc_inc3.vh" 1
verilog/t_preproc_inc3.vh:1: `line 2 "inc3_a_filename_from_line_directive" 0
inc3_a_filename_from_line_directive:10:  At file "inc3_a_filename_from_line_directive" line 10
inc3_a_filename_from_line_directive:19: `line 19 "inc3_a_filename_from_line_directive" 2
verilog/inc2.v:5: `line 5 "verilog/inc2.v" 0
verilog/inc2.v:7: `line 7 "verilog/inc2.v" 2
verilog/inc1.v:1: `line 1 "verilog/inc1.v" 0
verilog/inc1.v:4:  text.
verilog/inc1.v:15:  wire [3:0] q = {
verilog/inc1.v:16:    1'b1    ,
verilog/inc1.v:17:      1'b0  ,
verilog/inc1.v:18:    1'b1    ,
verilog/inc1.v:19:      1'b0 
verilog/inc1.v:20:  };
verilog/inc1.v:22: text.
verilog/inc1.v:26: foo   bar  
verilog/inc1.v:27: foobar2
verilog/inc1.v:39: first part 
verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0
verilog/inc1.v:39:  second part 
verilog/inc1.v:39: `line 39 "verilog/inc1.v" 0
verilog/inc1.v:39:  third part
verilog/inc1.v:40: {
verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0
verilog/inc1.v:40:  a,
verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0
verilog/inc1.v:40:  b,
verilog/inc1.v:40: `line 40 "verilog/inc1.v" 0
verilog/inc1.v:40:  c}
verilog/inc1.v:41: Line_Preproc_Check 41
verilog/inc1.v:49: deep deep
verilog/inc1.v:53: "Inside: `nosubst"
verilog/inc1.v:54: "`nosubst"
verilog/inc1.v:57: x y LLZZ x y
verilog/inc1.v:58: p q LLZZ p q r s LLZZ r s LLZZ p q LLZZ p q r s LLZZ r s
verilog/inc1.v:62: firstline comma","line LLZZ firstline comma","line
verilog/inc1.v:65: x y LLZZ "x" y  
verilog/inc1.v:68: (a,b)(a,b)
verilog/inc1.v:71: $display("left side: \"right side\"")
verilog/inc1.v:74: bar_suffix more
verilog/inc1.v:78: `line 78 "verilog/inc1.v" 0
verilog/inc1.v:78:  $c("Zap(\"",bug1,"\");");;
verilog/inc1.v:79: `line 79 "verilog/inc1.v" 0
verilog/inc1.v:79:  $c("Zap(\"","bug2","\");");;
verilog/inc1.v:93:  initial begin
verilog/inc1.v:95:  $display("pre thrupre thrumid thrupost post: \"right side\"");
verilog/inc1.v:96:  $display("left side: \"right side\"");
verilog/inc1.v:97:  $display("left side: \"right side\"");
verilog/inc1.v:98:  $display("left_side: \"right_side\"");
verilog/inc1.v:99:  $display("na: \"right_side\"");
verilog/inc1.v:100:  $display("prep ( midp1 left_side midp2 ( outp ) ): \"right_side\"");
verilog/inc1.v:101:  $display("na: \"nana\"");
verilog/inc1.v:102:  $display("left_side right_side: \"left_side right_side\"");  
verilog/inc1.v:103:  $display(": \"\"");  
verilog/inc1.v:104:  $display("left side: \"right side\"");
verilog/inc1.v:105:  $display("left side: \"right side\"");
verilog/inc1.v:106:  $display("standalone");
verilog/inc1.v:111:  $display("twoline: \"first        second\"");
verilog/inc1.v:113:  $write("*-* All Finished *-*\n");
verilog/inc1.v:114:  $finish;
verilog/inc1.v:115:  end
verilog/inc1.v:116: endmodule
verilog/inc1.v:126: module add1 ( input wire d1, output wire o1);
verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0
verilog/inc1.v:127: wire tmp_d1 = d1; 
verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0
verilog/inc1.v:127: wire tmp_o1 = tmp_d1 + 1; 
verilog/inc1.v:127: `line 127 "verilog/inc1.v" 0
verilog/inc1.v:127: assign o1 = tmp_o1 ;  
verilog/inc1.v:128: endmodule
verilog/inc1.v:129: module add2 ( input wire d2, output wire o2);
verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0
verilog/inc1.v:130: wire tmp_d2 = d2; 
verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0
verilog/inc1.v:130: wire tmp_o2 = tmp_d2 + 1; 
verilog/inc1.v:130: `line 130 "verilog/inc1.v" 0
verilog/inc1.v:130: assign o2 = tmp_o2 ;  
verilog/inc1.v:131: endmodule
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144:  generate for (i=0; i<(3); i=i+1) begin 
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144:  psl cover { m5k.f .ctl._ctl_mvldx_m1.d[i] & ~m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoRise: m5kc_fcl._ctl_mvldx_m1"; 
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144:  psl cover { ~m5k.f .ctl._ctl_mvldx_m1.d[i] & m5k.f .ctl._ctl_mvldx_m1.q[i] & !m5k.f .ctl._ctl_mvldx_m1.cond & ((m5k.f .ctl.alive & m5k.f .ctl.alive_m1))} report "fondNoFall: m5kc_fcl._ctl_mvldx_m1"; 
verilog/inc1.v:144: `line 144 "verilog/inc1.v" 0
verilog/inc1.v:144:  end endgenerate  
verilog/inc1.v:148: module prot();
verilog/inc1.v:149: `protected
verilog/inc1.v:150:     I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
verilog/inc1.v:151:     #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
verilog/inc1.v:152: `endprotected
verilog/inc1.v:153: endmodule
verilog/inc1.v:155: module prot2();
verilog/inc1.v:156: `pragma protect begin_protected
verilog/inc1.v:157: `pragma protect encrypt_agent = "Whatever agent"
verilog/inc1.v:158: `pragma protect encrypt_agent_info = "1.2.3"
verilog/inc1.v:159: `pragma protect data_method = "aes128-cbc"
verilog/inc1.v:160: `pragma protect key_keyowner = "Someone"
verilog/inc1.v:161: `pragma protect key_keyname = "somekey", key_method = "rsa"
verilog/inc1.v:162: `pragma protect key_block encoding = (enctype = "base64")
verilog/inc1.v:163:    wefjosdfjklajklasjkl
verilog/inc1.v:164: `pragma protect data_block encoding = (enctype = "base64", bytes = 1059)
verilog/inc1.v:165:     I!#r#e6<_Q{{E2+]I3<[3s)1@D|'E''i!O?]jD>Jo_![Cl)
verilog/inc1.v:166:     #nj1]p,3^1~,="E@QZB\T)eU\pC#C|7=\$J$##A[@-@{Qk]
verilog/inc1.v:167: `pragma protect end_protected
verilog/inc1.v:168: `pragma reset protect
verilog/inc1.v:169: endmodule
verilog/inc1.v:181: begin addr <= (({regs[6], regs[7]} + 1)); rd <= 1; end and begin addr <= (({regs[6], regs[7]})); wdata <= (rdata); wr <= 1; end
verilog/inc1.v:182: begin addr <= ({regs[6], regs[7]} + 1); rd <= 1; end
verilog/inc1.v:183: begin addr <= ({regs[6], regs[7]}); wdata <= (rdata); wr <= 1; end more
verilog/inc1.v:188: `line 188 "verilog/inc1.v" 0
verilog/inc1.v:188: `line 1 "verilog/t_preproc_inc4.vh" 1
verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0
verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2
verilog/inc1.v:188: `line 188 "verilog/inc1.v" 0
verilog/inc1.v:202: $blah("ab,cd","e,f");
verilog/inc1.v:203: $blah(this.logfile,vec);
verilog/inc1.v:204: $blah(this.logfile,vec[1,2,3]);
verilog/inc1.v:205: $blah(this.logfile,{blah.name(), " is not foo"});
verilog/inc1.v:210: `pragma foo = 1
verilog/inc1.v:211: `default_nettype none
verilog/inc1.v:212: `default_nettype uwire
verilog/inc1.v:221: Line_Preproc_Check 221
verilog/inc1.v:229: (p,q)
verilog/inc1.v:233: (x,y)
verilog/inc1.v:234: Line_Preproc_Check 234
verilog/inc1.v:243: beginend  
verilog/inc1.v:244: beginend  
verilog/inc1.v:245: "beginend"  
verilog/inc1.v:251:  `\esc`def
verilog/inc1.v:253: Not a \`define
verilog/inc1.v:261: x,y)--bee submacro has comma paren
verilog/inc1.v:266: $display("10 %d %d", $bits(foo), 10);
verilog/inc1.v:290: `line 290 "verilog/inc1.v" 0
verilog/inc1.v:290: `line 290 "verilog/inc1.v" 0
verilog/inc1.v:290: `line 290 "verilog/inc1.v" 0
verilog/inc1.v:290: `line 290 "verilog/inc1.v" 0
verilog/inc1.v:290: `line 290 "verilog/inc1.v" 0
verilog/inc1.v:290: `line 290 "verilog/inc1.v" 0
verilog/inc1.v:290: `line 290 "verilog/inc1.v" 0
verilog/inc1.v:290: `line 290 "verilog/inc1.v" 0
verilog/inc1.v:290: `line 290 "verilog/inc1.v" 0
verilog/inc1.v:290:  assign a3 = ~b3 ; 
verilog/inc1.v:290: `line 290 "verilog/inc1.v" 0
verilog/inc1.v:292: `line 292 "verilog/inc1.v" 0
verilog/inc1.v:293:   \
verilog/inc1.v:294: `line 294 "verilog/inc1.v" 0
verilog/inc1.v:301: `line 301 "verilog/inc1.v" 0
verilog/inc1.v:301: `line 301 "verilog/inc1.v" 0
verilog/inc1.v:301: `line 301 "verilog/inc1.v" 0
verilog/inc1.v:301:  def i 
verilog/inc1.v:301: `line 301 "verilog/inc1.v" 0
verilog/inc1.v:315: 1  (nodef)
verilog/inc1.v:316: 2   (hasdef)
verilog/inc1.v:317: 3  (nodef)
verilog/inc1.v:318: 4 
verilog/inc1.v:318: `line 318 "verilog/inc1.v" 0
verilog/inc1.v:318:   (nodef)
verilog/inc1.v:319: 5 also in 
verilog/inc1.v:319: `line 319 "verilog/inc1.v" 0
verilog/inc1.v:319:  also3 (nodef)
verilog/inc1.v:322: HAS a NEW 
verilog/inc1.v:322: `line 322 "verilog/inc1.v" 0
verilog/inc1.v:322: LINE
verilog/inc1.v:342: EXP: clxx_scen
verilog/inc1.v:343: clxx_scen
verilog/inc1.v:344: EXP: clxx_scen
verilog/inc1.v:345: "clxx_scen"
verilog/inc1.v:347: EXP: do if (start("verilog/inc1.v", 25)) begin message({"Blah-", "clx_scen", " end"}); end while(0);
verilog/inc1.v:348: `line 348 "verilog/inc1.v" 0
verilog/inc1.v:348:  do 
verilog/inc1.v:348: `line 348 "verilog/inc1.v" 0
verilog/inc1.v:348: `line 348 "verilog/inc1.v" 0
verilog/inc1.v:348:  while(0);
verilog/inc1.v:356: `line 356 "verilog/inc1.v" 0
verilog/inc1.v:356: `line 356 "verilog/inc1.v" 0
verilog/inc1.v:356: `line 356 "verilog/inc1.v" 0
verilog/inc1.v:359: EXP: This is fooed
verilog/inc1.v:360: This is fooed
verilog/inc1.v:361: EXP: This is fooed_2
verilog/inc1.v:362: This is fooed_2
verilog/inc1.v:366: np
verilog/inc1.v:367: np
verilog/inc1.v:390: hello3hello3hello3
verilog/inc1.v:391: hello4hello4hello4hello4
verilog/inc1.v:396: `line 396 "verilog/inc1.v" 0
verilog/inc1.v:396: `line 1 "verilog/t_preproc_inc4.vh" 1
verilog/t_preproc_inc4.vh:2: `line 2 "verilog/t_preproc_inc4.vh" 0
verilog/t_preproc_inc4.vh:7: `line 7 "verilog/t_preproc_inc4.vh" 2
verilog/inc1.v:396: `line 396 "verilog/inc1.v" 0
verilog/inc1.v:405: `line 405 "verilog/inc1.v" 0
verilog/inc1.v:409: Line_Preproc_Check 409
verilog/inc1.v:415: Line_Preproc_Check 415
verilog/inc1.v:417: "FOO \
verilog/inc1.v:417:   BAR " "arg_line1 \
verilog/inc1.v:417:   arg_line2" "FOO \
verilog/inc1.v:417:   BAR "
verilog/inc1.v:418: `line 418 "verilog/inc1.v" 0
verilog/inc1.v:418: Line_Preproc_Check 418
verilog/inc1.v:427: abc
verilog/inc1.v:435: EXP: sonet_frame
verilog/inc1.v:436: sonet_frame
verilog/inc1.v:440: EXP: sonet_frame
verilog/inc1.v:441: sonet_frame
verilog/inc1.v:445: EXP: sonet_frame
verilog/inc1.v:446: sonet_frame
verilog/inc1.v:451: EXP: module zzz ; endmodule
verilog/inc1.v:452: module zzz ; endmodule
verilog/inc1.v:453: module zzz ; endmodule
verilog/inc1.v:456: EXP: module a_b ; endmodule
verilog/inc1.v:457: module a_b ; endmodule
verilog/inc1.v:458: module a_b ; endmodule
verilog/inc1.v:462: integer foo;
verilog/inc1.v:464: synth_test:
verilog/inc1.v:465: `line 465 "verilog/inc1.v" 0
verilog/inc1.v:468: EXP: on
verilog/inc1.v:471: module t;
verilog/inc1.v:478:  initial begin : \`LEX_CAT(a[0],_assignment) 
verilog/inc1.v:478: `line 478 "verilog/inc1.v" 0
verilog/inc1.v:478:  $write("GOT%%m='%m' EXP='%s'\n", "t.\\`LEX_CAT(a[0],_assignment) "); end
verilog/inc1.v:485:  initial begin : \a[0]_assignment_a[1] 
verilog/inc1.v:485: `line 485 "verilog/inc1.v" 0
verilog/inc1.v:485:  $write("GOT%%m='%m' EXP='%s'\n", "t.\\a[0]_assignment_a[1] "); end
verilog/inc1.v:492:  initial begin : \`CAT(pp,suffix) $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(pp,suffix) "); end
verilog/inc1.v:499:  initial begin : \`CAT(ff,bb) 
verilog/inc1.v:499: `line 499 "verilog/inc1.v" 0
verilog/inc1.v:499:  $write("GOT%%m='%m' EXP='%s'\n", "t.\\`CAT(ff,bb) "); end
verilog/inc1.v:505:  initial begin : \`zzz 
verilog/inc1.v:505: `line 505 "verilog/inc1.v" 0
verilog/inc1.v:505:  $write("GOT%%m='%m' EXP='%s'\n", "t.\\`zzz "); end
verilog/inc1.v:512:  initial begin : \`FOO 
verilog/inc1.v:512: `line 512 "verilog/inc1.v" 0
verilog/inc1.v:512:  $write("GOT%%m='%m' OTHER_EXP='%s'\n OUR_EXP='%s'", "t.bar ","t.\\`FOO "); end
verilog/inc1.v:514:  initial begin : \xx`FOO 
verilog/inc1.v:514: `line 514 "verilog/inc1.v" 0
verilog/inc1.v:514:  $write("GOT%%m='%m' EXP='%s'\n", "t.\\xx`FOO "); end
verilog/inc1.v:519:  initial begin : \`UNKNOWN $write("GOT%%m='%m' EXP='%s'\n", "t.\\`UNKNOWN "); end
verilog/inc1.v:523:  initial begin : \`DEF_NO_EXPAND $write("GOT%%m='%m' EXP='%s'\n", "t.\\`DEF_NO_EXPAND "); end
verilog/inc1.v:529:  initial $write("GOT='%s' EXP='%s'\n", "foo bar baz", "foo bar baz");
verilog/inc1.v:535:  initial $write("GOT='%s' EXP='%s'\n", "foo `A(bar) baz", "foo `A(bar) baz");
verilog/inc1.v:540:  initial $write("Slashed=`%s'\n", "1//2.3");
verilog/inc1.v:545:  initial 
verilog/inc1.v:545: `line 545 "verilog/inc1.v" 0
verilog/inc1.v:545:  $display("%s%s","a1","b2c3\n");
verilog/inc1.v:546: endmodule
verilog/inc1.v:553: $display("RAM0");
verilog/inc1.v:554: $display("CPU");
verilog/inc1.v:562: XXE_FAMILY = XXE_
verilog/inc1.v:565:  $display("XXE_ is defined");
verilog/inc1.v:569: XYE_FAMILY = XYE_
verilog/inc1.v:572:  $display("XYE_ is defined");
verilog/inc1.v:576: XXS_FAMILY = XXS_some
verilog/inc1.v:579:  $display("XXS_some is defined");
verilog/inc1.v:583: XYS_FAMILY = XYS_foo
verilog/inc1.v:586:  $display("XYS_foo is defined");
verilog/inc1.v:626: (.mySig (myInterface.pa5),
verilog/inc1.v:631: predef 0 0
verilog/inc1.v:632: predef 1 1
verilog/inc1.v:633: predef 2 2
verilog/inc1.v:634: predef 3 3
verilog/inc1.v:635: predef 10 10
verilog/inc1.v:636: predef 11 11
verilog/inc1.v:637: predef 20 20
verilog/inc1.v:638: predef 21 21
verilog/inc1.v:639: predef 22 22
verilog/inc1.v:640: predef 23 23
verilog/inc1.v:641: predef -2 -2
verilog/inc1.v:642: predef -1 -1
verilog/inc1.v:643: predef 0 0
verilog/inc1.v:644: predef 1 1
verilog/inc1.v:645: predef 2 2
verilog/inc1.v:647: `line 647 "verilog/inc1.v" 2