SystemC::Netlist - SystemC Netlist
use SystemC::Netlist; # See Verilog::Netlist for base functions $nl->autos(); $nl->exit_if_error();
SystemC::Netlist contains interconnect information about a whole design database. The classes of SystemC::Netlist parallel those of Verilog::Netlist, which should be seen for all documentation.
The database is composed of files, which contain the text read from each file.
A file may contain modules, which are individual blocks that can be instantiated (designs, in Synopsys terminology.)
Modules have ports, which are the interconnection between nets in that module and the outside world. Modules also have nets, (aka signals), which interconnect the logic inside that module.
Modules can also instantiate other modules. The instantiation of a module is a Cell. Cells have pins that interconnect the referenced module's pin to a net in the module doing the instantiation.
Each of these types, files, modules, ports, nets, cells and pins have a class. For example SystemC::Netlist::Cell has the list of SystemC::Netlist::Pin (s) that interconnect that cell.
See Verilog::Netlist for all common functions.
Updates /*AUTO*/ comments in the internal database. Normally called before lint.
Return the version number of SystemC.
Copyright 2001-2013 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
Wilson Snyder <email@example.com>
SystemC::Netlist::Cell, SystemC::Netlist::Class, SystemC::Netlist::CoverGroup, SystemC::Netlist::File, SystemC::Netlist::Module, SystemC::Netlist::Net, SystemC::Netlist::Pin, SystemC::Netlist::Port, Verilog::Netlist::Subclass