Wilson Snyder > Verilog-Perl-3.318 > Verilog::Netlist::Pin



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Module Version: 3.318   Source   Latest Release: Verilog-Perl-3.418


Verilog::Netlist::Pin - Pin on a Verilog Cell


  use Verilog::Netlist;

  my $pin = $cell->find_pin ('pinname');
  print $pin->name;


A Verilog::Netlist::Pin object is created by Verilog::Netlist::Cell for for each pin connection on a cell. A Pin connects a net in the current design to a port on the instantiated cell's module.


See also Verilog::Netlist::Subclass for additional accessors and methods.


Reference to the Verilog::Netlist::Cell the pin is under.


Returns any comments following the definition. keep_comments=>1 must be passed to Verilog::Netlist::new for comments to be retained.


Delete the pin from the cell it's under.


Reference to the Verilog::Netlist::Module the pin is in.


The name of the pin. May have extra characters to make vectors connect, generally portname is a more readable version. There may be multiple pins with the same portname, only one pin has a given name.


Reference to the Verilog::Netlist::Net the pin connects to. Only valid after a link.


Reference to the Verilog::Netlist the pin is in.


The net name the pin connects to.


The name of the port connected to.


Reference to the Verilog::Netlist::Port the pin connects to. Only valid after a link.


See also Verilog::Netlist::Subclass for additional accessors and methods.


Checks the pin for errors. Normally called by Verilog::Netlist::lint.


Prints debugging information for this pin.


Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

Copyright 2000-2012 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.


Wilson Snyder <wsnyder@wsnyder.org>


Verilog-Perl, Verilog::Netlist::Subclass Verilog::Netlist

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