Wilson Snyder > Verilog-Perl-3.318 > Verilog::Std

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Module Version: 3.318   Source   Latest Release: Verilog-Perl-3.406

NAME ^

Verilog::Std - SystemVerilog Built-in std Package Definition

SYNOPSIS ^

Internally used by Verilog::SigParser, etc.

   use Verilog::Std;
   print Verilog::Std::std;

DESCRIPTION ^

Verilog::Std contains the built-in "std" package required by the SystemVerilog standard.

FUNCTIONS ^

std ({standard})

Return the definition of the std package. Optionally pass the language standard, defaulting to what Verilog::Language::language_standard returns if unspecified.

DISTRIBUTION ^

Verilog-Perl is part of the http://www.veripool.org/ free Verilog EDA software tool suite. The latest version is available from CPAN and from http://www.veripool.org/verilog-perl.

Copyright 2009-2012 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.

AUTHORS ^

Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO ^

Verilog-Perl

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