Verilog::Std - SystemVerilog Built-in std Package Definition
Internally used by Verilog::SigParser, etc.
use Verilog::Std; print Verilog::Std::std;
Verilog::Std contains the built-in "std" package required by the SystemVerilog standard.
Return the definition of the std package. Optionally pass the language standard, defaulting to what Verilog::Language::language_standard returns if unspecified.
Copyright 2009-2018 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License Version 3 or the Perl Artistic License Version 2.0.
Wilson Snyder <firstname.lastname@example.org>