Wilson Snyder > Verilog-Pli-1.703 > Verilog::Pli::Net

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Module Version: 1.703   Source  

NAME ^

Verilog::Pli::Net - Verilog PLI tied net access hash

SYNOPSIS ^

  use Verilog::Pli::Net;

  $NET{"hier.signal"} = 1;
  print "Signal now is ", $NET{"hier.signal"};
  foreach (keys %NET) { print "Found signal $_\n"; }
  (exists $NET{"bad"}) or die "Net 'bad' doesn't exist.";

  tie %PLINET, 'Verilog::Pli::Net', 'top.hier.submod.pli;
  print "top.hier.submod.pli.something = ", $PLINET{"something"}, "\n";

DESCRIPTION ^

This package creates a tied hash %NET, that fetching from or storing to affects the Verilog signal named the same as the hash key. The hierarchy may be placed in front of the signal names using standard dot notation, or if not found, the scope from when the tie was established, or later scope() calls is prepended to the passed signal name.

Signal names may have a leading %b: %d: %x: or %s: to return or set the value in the binary, decimal, hex, or string format respectively. Values may have a leading 0b or 0x to set the value in binary or hex format respectively.

scope

Read or change the default scope used when a signal is not found with the name passed. Note you need to pass the class, use the tied function to convert from the tied hash to the class name.

DISTRIBUTION ^

The latest version is available from CPAN or http://www.veripool.com/.

Copyright 1998-2007 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.

AUTHORS ^

Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO ^

Verilog::Pli

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