Wilson Snyder > Verilog-Pli-1.703 > Verilog::Pli

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Module Version: 1.703   Source  

NAME ^

Verilog::Pli - Verilog PLI routine calls

SYNOPSIS ^

  use Verilog::Pli;

DESCRIPTION ^

This package allows access to Verilog PLI routines from perl. See the Verilog PLI Reference Manual for more information on these functions.

This package has only been tested with VCS. It should work with other simulators, though different header files may need to be included.

mc_scan_plusargs (switch)

Return string if switch is set on command line.

Verilog::Pli::io_printf (format, arg1)

Print a string using Verilog I/O. Try to use Verilog::Pli::IO instead of this routine.

tf_dofinish

Finish the simulation.

tf_dostop

Stop the simulation.

tf_gettime

Return simulation time.

tf_igettime

Return simulation time for the passed instance.

tf_getinstance

Return the current instance.

DISTRIBUTION ^

The latest version is available from CPAN or http://www.veripool.com/.

Copyright 1998-2007 by Wilson Snyder. This package is free software; you can redistribute it and/or modify it under the terms of either the GNU Lesser General Public License or the Perl Artistic License.

AUTHORS ^

Wilson Snyder <wsnyder@wsnyder.org>

SEE ALSO ^

Verilog::Pli::IO, Verilog::Pli::Net

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