Wim Vanderbauwhede > Verilog-CodeGen-0.9.4 > Verilog::Codegen::Gui

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NAME ^

Verilog::Codegen::Gui - Verilog code generator GUI

SYNOPSIS ^

  $ ./gui.pl [design name]

The GUI and its utility scrips are in the scripts folder of the distribution.

The design name is optional. If no design name is provided, the GUI will check the .vcgrc file for one. If this file does not exists, the design library module defaults to DeviceLibs/Verilog.pm and the objects will reside directly under DeviceLibs/Objects. Otherwise, the design library module will be DeviceLibs/YourDesign.pm and the objects will reside under DeviceLibs/YourDesign/Objects. You can also set the design name via the GUI.

USAGE ^

The GUI is very simple to use. A short manual:

To create, test and run Verilog code using the Verilog::CodeGen GUI:

0. Choose your design.

In the Design text entry field, type the full name of the design. Click Set.

If the design does not exist, it will be created, that is, an empty structure with skeleton files will be created. Otherwise, the design will be set to the entered value.

1. Create or edit the Device Object.

This is the Perl script that will generate the Verilog code.

2. Test the object code

In the Device Object Code area, click Parse. This executes the script and displays the output in the Output log window. Ticking the Show result tick box will cause the output to be displayed in an XEmacs window. To close this window, click Done. This is a modal window, in other words it will freeze the main display as long as it stays open.

3. Add the Device Object to the Device Library

When the object code is bug finished, click Update in the Device Library Module area. This will add the device object to the device library (which is a Perl module). Ticking the Show module tick box will cause the complete library module to be displayed in an XEmacs window. To close this window, click Done. This is a modal window, in other words it will freeze the main display as long as it stays open.

4. Create or edit the test bench code

This is the Perl script that will generate the Verilog testbench code.

5. Test the testbench code

In the Testbench Code area, click Parse. This executes the script and displays the output in the Output log window.

-Ticking the Show result tick box will cause the output to be displayed in an XEmacs window. To close this window, click Done. This is a modal window, in other words it will freeze the main display as long as it stays open.

-Ticking the Inspect code tick box will open a browser window with pages generated by the v2html Verilog to HTML convertor.

-Ticking the Run tick box will execute the generated testbench.

-Ticking the Plot tick box will plot the simulation results (if any exist).

REQUIREMENTS ^

To use a different Verilog compiler/simulator and/or VCD viewer:

In CodeGen.pm, change the following lines:

   #Modify this to use different compiler/simulator/viewer
   my $compiler="/usr/bin/iverilog";
   my $simulator="/usr/bin/vvp";
   my $vcdviewer="/usr/local/bin/gtkwave";

TODO ^

AUTHOR ^

W. Vanderbauwhede wim@motherearth.org.

http://www.comms.eee.strath.ac.uk/~wim

COPYRIGHT ^

Copyright (c) 2002,2003 Wim Vanderbauwhede. All rights reserved. This program is free software; you can redistribute it and/or modify it under the same terms as Perl itself.

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